Basic DRAM operation

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Basic DRAM operation

Before a computer can perform any useful task, it copies applications and data from the hard disk drive to the system memory. Computers use two types of system memory—cache memory and main memory. Cache memory consists of very fast static RAM (SRAM) and is usually integrated with the processor. Main memory consists of DRAM chips on dual inline memory modules (DIMMs) that can be packaged in various ways depending on system form factor.

Each DRAM chip contains millions of memory locations (or cells), which are arranged in a matrix of rows and columns (Figure 1). Peripheral circuitry on the DIMM reads, amplifies, and transfers the data from the memory cells to the memory bus. Each DRAM row, called a page, consists of several DRAM cells. Each DRAM cell on a page contains a capacitor capable of storing an electrical charge for a very short time. A charged cell represents a “1” data bit, and an uncharged cell represents a “0” data bit. To prevent the capacitors from discharging, they must be recharged (refreshed) thousands of times per second to maintain the validity of the data. Refresh mechanisms are described later in this section.

The memory subsystem operates at the memory bus speed. Typically, to access a DRAM cell, the memory controller sends electronic address signals that specify the row address and column address of the target cell. The memory controller sends these signals to the DRAM chip by way of the memory bus. The memory bus consists of two sub-buses: the address/command bus and the data bus.

The data bus is a set of lines (traces) that carry the data to and from DRAM. Each trace carries one data bit at a time. The throughput (bandwidth) of the data bus depends on its width (in bits) and its frequency. The data width of a memory bus is usually 64-bits, which means that the bus has 64 traces, each of which transports one bit at a time. Each 64-bit unit of data is called a data word.

The address portion of the address/command bus is a set of traces that carry signals identifying the location of data in memory. The command portion of the address/command bus conveys instructions such as read, write, or refresh.

When FPM or EDO memory writes data to a particular cell, the memory controller selects the location in which to write the data. The memory controller first selects the page by strobing the Row Address onto the address/command bus. It then selects the exact location by strobing the Column Address onto the address/command bus (see Figure 2). These actions are called Row Address Strobe (RAS) and Column Address Strobe (CAS). The Write Enable (WE) signal is activated at the same time as the CAS to specify that a write operation is to be performed. The memory controller then drives the data onto the memory bus. The DRAM devices capture (latch) the data and store it into the respective cells.

During a DRAM read operation, RAS followed by CAS are driven onto the memory bus. The WE signal is held inactive, indicating a read operation. After a delay called CAS Latency, the DRAM devices drive the data onto the memory bus.

DRAM cannot be accessed during a refresh. If the processor makes a data request during a DRAM refresh, the data will not be available until the refresh completes. There are many mechanisms to refresh DRAM, including RAS only refresh, CAS before RAS (CBR) refresh, and Hidden refresh. CBR, which involves driving CAS active before driving RAS active, is used most often.

Information porvided by Hewlett-Packard Development Company, L.P.