FB-DIMM : Fully-Buffered DIMM architecture

TIM

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Fully-Buffered DIMM architecture

The FB-DIMM architecture has serial links between the memory controller and the FB-DIMMs, which are connected in a daisy chain configuration (Figure 3). Relative to the memory controller, there are 10 outbound links and 14 inbound links, also known as southbound and northbound links, respectively. These serial links connect the memory controller to an advanced memory buffer (AMB) chip that resides on each FB-DIMM, creating a point-to-point architecture. The outbound links transmit commands and write data to the FB-DIMMs while the inbound links transmit read data back to the memory controller.

The clock signal is distributed over a different set of pins, and the memory controller communicates with each AMB over the SMBus.

The AMB is an intelligent chip that manages serial communication with the memory controller and parallel communication with local DRAM devices (Figure 4). Each AMB receives signals (address, write data, and command information) through the outbound links and re-transmits the signal to the next FB-DIMM on the channel. Each AMB decodes the command data and ignores the commands that are targeted for a different DIMM. The targeted AMB performs a read or write operation to local DRAM devices through a parallel interface. In the case of a read operation, the AMB serializes data from the DRAM devices and transmits it to the memory controller through the inbound links.

Inbound and outbound serial information is transmitted in packets, or frames. Each inbound frame is 18 bytes long (16 bytes of read data plus 2 bytes of ECC). The FB-DIMM channel clock operates at 6 times the speed of the DRAM clock so that one inbound frame to be transmitted in a single DRAM clock cycle. The 6:1 clock ratio allows the data rate of the DRAM module to match the data rate of the inbound link. For example, when using DDR2 533 DRAM on the FB-DIMM, the peak theoretical throughput of both the DRAM devices and the inbound links is 4.3 GB/sec.

Each outbound frame is 120 bits (15 bytes) long and consists of a command and 9 bytes of write data (8 bytes plus 1 byte of ECC). Note that the outbound links transport half the amount of data as the inbound links per DRAM clock cycle (9 bytes compared to 18 bytes).

Information provided by Hewlett-Packard Development Company, L.P.