Each DRAM chip on a DIMM provides either 4 bits or 8 bits of a 64-bit data word. Chips that provide 4 bits are called x4 (by 4), and chips that provide 8 bits are called x8 (by . It takes eight x8 chips or sixteen x4 chips to make a 64-bit word, so at least eight chips are located on one or both sides of a DIMM. However, a standard DIMM has enough room to hold a ninth chip on each side. The ninth chip is used to store 4 bits or 8 bits of Error Correction Code (ECC).
An ECC DIMM with all nine DRAM chips on one side is called single-sided, and an ECC DIMM with nine DRAM chips on each side is called double-sided (Figure 7). A single-sided x8 ECC DIMM and a double-sided x4 ECC DIMM each create a single block of 72 bits (64 bits plus 8 ECC bits). In both cases, a single chip-select signal from the memory controller activates all the chips on the DIMM. In contrast, a double-sided x8 DIMM (bottom illustration) requires two chip-select signals to access two 72-bit blocks on two sets of DRAM chips.
Single-rank, dual-rank, and quad-rank DIMMs
In addition to single-sided and double-sided configurations, DIMMs are classified as to rank. A memory rank is defined as an area or block of 64-bits (72 bits for ECC memory) created by using some or all of the DRAM chips on a DIMM.
A single-rank ECC DIMM (x4 or x uses all of its DRAM chips to create a single block of 72 bits, and all the chips are activated by one chip-select (CS) signal from the memory controller (top two illustrations in Figure 7). A dual-rank ECC DIMM produces two 72-bit blocks from two sets of DRAM chips on the DIMM, requiring two chip-select signals. The chip-select signals are staggered so that both sets of DRAM chips do not contend for the memory bus at the same time. Quad-rank DIMMs with ECC produce four 72-bit blocks from four sets of DRAM chips on the DIMM, requiring four chip-select signals. Like the dual-rank DIMMs, the memory controller staggers the chip-select signals to prevent the four sets of DRAM chips from contending for the memory bus at the same time.
Memory ranks are not new, but their role has become more critical with the advent of new chipset and memory technologies and growing server memory capacities. Dual-rank DIMMs improve memory density by placing the components of two single-rank DIMMs in the space of one module. The chipset considers each rank as an electrical load on the memory bus. At slower bus speeds, the number of loads does not adversely affect bus signal integrity. However, for faster memory technologies such as DDR2-667, there is a maximum number of ranks that the chipset can drive. For example, if a memory bus on a server has four DIMM slots, the chipset may only be capable of supporting two dual-rank DIMMs or four single rank DIMMs. If two dual-rank DIMMs are installed, then the last two slots must not be populated. To compensate for the reduction in the number of DIMM slots on a bus at higher speeds, modern chipsets employ multiple memory buses.
If the total number of ranks in the populated DIMM slots exceeds the maximum number of loads the chipset can support, the server may not boot properly or it may not operate reliably. Some systems check the memory configuration while booting to detect invalid memory bus loading. When an invalid memory configuration is detected, the system stops the boot process to avoid unreliable operation.
To prevent this and other memory-related problems, HP urges customers to use only HP-certified DIMMs, which are available in the memory option kits for each ProLiant server (see the Importance of using HP-certified memory modules in ProLiant servers section).
Another important difference between single-rank and dual-rank DIMMs is cost. Typically, memory costs increase with DRAM density. For example, the cost of an advanced, high-density DRAM chip is typically more than twice that of a conventional DRAM chip. Because large capacity single-rank DIMMs are manufactured with higher-density DRAM chips, they typically cost more than dual-rank DIMMs of comparable capacity.
Information porvided by Hewlett-Packard Development Company, L.P.
Figure 7. Single-sided and double-sided DDR SDRAM DIMMs and corresponding DIMM rank
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